In the field of semiconductor manufacturing, photoresist is often used to transfer patterns on a photomask into one or more layers of materials. For example, the patterns of the photomasks can be transferred into metal material layer(s), dielectric material layer(s), or semiconductor substrate(s), etc. With the continuously shrinking of the critical dimension (CD) of the semiconductor technology, it has become more and more difficult to form the photomask patterns with a substantially small CD into the material layer(s) using a photolithography process.
In order to reduce the optical proximity effect caused by the substantially small CD during the photolithography process, resolution enhancement techniques (RETs) have been developed. The RETs include the scattering bar technology, the phase-shift mask technology, the double patterning technology (DPT), and the triple patterning technology (TPT), etc. Amongst of these RETs, the DPT and the TPTs are considered as effective methods to bridge the gap between the immersion lithography and the extreme ultraviolet lithography. Comparing with the DPT, the TPT may obtain a smaller CD and a higher device pattern density, thus it has been used more and more often.
FIGS. 1˜4 illustrate an existing triple patterning process. As shown in FIG. 1, the triple patterning process includes providing a substrate 100; forming a plurality of discrete first patterns 101; and forming first sidewall spacers 102 on side surfaces of the first patterns 101.
Further, as shown in FIG. 2, the triple pattering process also includes forming a material layer 103 covering the substrate 100, the first sidewall spacers 102 and the first patterns 101.
Further, as shown in FIG. 3, the triple patterning process also includes etching the material layer 103 by a mask-less etching process to form second sidewall spacers 104 on the side surfaces of the first sidewall spacers 102.
Further, as shown in FIG. 4, the triple pattering process also includes removing the first sidewalls spacers 102; and the remaining first patterns 101 and the second sidewall spacers 104 form the triple patterns 105.
However, such a triple patterning process may be limited in its applications, and may be unable to the match diversified needs of the semiconductor manufacturing. The disclosed device structures and methods are directed to solve one or more problems set forth above.